FPGA-Based Sub-Microsecond Multi-Key Arcade Matrix Debouncing

Microcontroller Polling vs. True Hardware Logic

In competitive arcade gaming, speed-run pods, and ninja agility timers, standard microcontroller firmware polls switch matrices at 100Hz–1000Hz. To suppress physical mechanical contact bounce, software debounce routines inject artificial delays of 10ms to 25ms. This introduces unavoidable input lag that players physically feel.

The PlayerLabs TurboLatency architecture delegates switch sampling to a dedicated Lattice iCE40 UltraPlus FPGA running at 12MHz. By executing parallel hardware debouncing state machines concurrently on 16 discrete channels, switch closures are qualified in 40 nanoseconds with zero CPU overhead.

Verilog HDL Debounce State Machine

module switch_debouncer #(
    parameter CLK_FREQ_HZ = 12000000,
    parameter DEBOUNCE_NS = 40
)(
    input  wire clk,
    input  wire rst_n,
    input  wire raw_switch,
    output reg  clean_switch
);
    reg [1:0] sync_pipeline;
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            sync_pipeline <= 2\x27b11;
            clean_switch  <= 1\x27b1;
        end else begin
            sync_pipeline <= {sync_pipeline[0], raw_switch};
            if (sync_pipeline == 2\x27b00) clean_switch <= 1\x27b0;
            else if (sync_pipeline == 2\x27b11) clean_switch <= 1\x27b1;
        end
    end
endmodule

1000Hz USB HID Descriptors and Full N-Key Rollover

Qualified switch states are pushed directly into a USB Full-Speed 1000Hz HID descriptor pipeline. Because every switch input has an independent parallel state machine, full N-Key Rollover (NKRO) is achieved without diode ghosting or blocking across simultaneous button slams.

Hardware Pinout & Signal Mapping